Graphene/ferroelectric hybrid devices (Vol. 42, No. 2)

The soaring demands on non-volatile memory for ultra-portable electronic devices have grown NAND flash into a multi-billion dollar business. As a Si-CMOS based technology, NAND flash provides the most aggressive scalability, closely following the-state-of-art semiconductor manufacturing process. NAND flash also takes advantage of its relatively simple floating-gate structure and seamless integration with Si-CMOS logics, leading to significant lower production cost over other competing non-volatile technologies such as FeRAM and MRAM.

Graphene, with its ultra-high mobility and almost unlimited scalability down to atomic scale, is considered now as one of the most promising candidates for replacing Si. Graphene-based non-volatile memory has also been demonstrated very recently. However, a seamless solution for integrating graphene transistors and non-volatile memory remains a challenge.

Here, Zheng et al. demonstrate the wafer-scale patterning and device operations of Cu-CVD graphene-ferroelectric field effect transistors (GFeFETs) on ferroelectric Pb(Zr_0.3Ti_0.7)O₃ (PZT) substrates, integrating both transistor and non-volatile memory functionalities on the same chip.

In the linear regime of PZT, ultra-low-voltage operations of GFeFETs within +/-1V can be used as controlling transistors for addressing and reading/writing of memory unit cells. After polarizing PZT, the hysteretic switching of GFeFETs is ideal for ultra-fast non-volatile data storage. The combination of high-quality Cu-CVD graphene and functional substrates will not only greatly speed up the studies of all graphene-based electronics but also open up a new route in exploring new graphene physics and functionalities.